1. Technical Field
The present disclosure relates to a probe card system for wireless testing of integrated devices.
More specifically, the disclosure relates to a probe card system of a testing apparatus for testing integrated devices comprising a plurality of elementary wireless coupling elements able to allow a wireless transmission between the probe card system and a device to be tested and the following description is made with reference to this field of application for convenience of explanation only.
2. Description of the Related Art
As is well known, the electric selection of devices carried out on wafer, i.e., the so called Electric Wafer Sort (EWS) testing, includes electrically connecting a tester or ATE (acronym of “Automated Test Equipment”) that executes measures on the wafer. A terminal portion of the testing apparatus is schematically shown in FIG. 1A, globally indicated with 1.
The wafer 6 includes a plurality of devices to be tested or selected, in particular chips 7 (also indicated as integrated circuits (IC). The interface between the ATE 1A and a wafer 6 is a so called probe card 2, which typically is a printed circuit board (PCB), and a probe head 3. The probe head 3 comprises different hundreds (several times thousands) of probes 4 that electrically connect the ATE 1A to almost all the contact pads 8 of a chip 7 to be tested, as shown in greater detail but always schematically in FIG. 1B. In particular, each end portion or tip 9 of the probes 4 comes into contact with a pad 8 of the chip 7 during a testing phase.
In general, the wafer 6 includes a plurality of chips 7 to be tested, and during the testing steps it is put on a support 5, shown in the portion of the testing apparatus 1, and belonging to an apparatus also called prober (not shown in the figure), this support 5 being thus also indicated as prober chuck.
The number of pads 8 for a testing can be smaller or equal to the total number of pads 8 of the chip 7 to be tested.
In a similar way, one goes further even if the chips 7 have bumps instead of pads 8, as it is well known to the technical experts in the field.
Before each chip 7 is encapsulated in a corresponding package, it is known that the testing of the chip 7 itself is executed, the chip 7 being still on the wafer 6, using the probes 4 that are connected directly to the pads 8 and that execute the so-called probing of the pad 8 they contact.
After the testing, the wafer 6 is cut and the chips 7 that have been tested and are operating are assembled in their package, ready for further process steps, also comprising further testing steps of the chips 7 in the package wherein they have been assembled.
In particular, similarly to the testing on wafer, the ATE is in particular able to execute a final test or FT (acronym of “Final Test”) of what is contained in a package, electrically connecting the connections of the package itself.
In the case of SiP systems (acronym of “System In Package”) there can be other situations, even very complex, further to the creation of electric connections between the various parts (chips, passive components, PCB, . . . ) of the system, these situations being well known to the technical experts in the field and in particular to the testing specialists.
It is also well known that a generic electronic system or chip is connected to the surrounding world through connections such as cabled channels (for example: cables, optical fibers, . . . ) or wireless channels, for example of the electromagnetic type. These connections allow to exchange information signals and/or to supply power to the same chips.
In case magnetic or electromagnetic signals are to be exchanged between an integrated circuit IC and at least another external system, the integrated circuit IC should have at least one receiver/transmitter inside. In the case of magnetic coupling these circuits are called transceiver/transponder, connected to at least one antenna that can be embedded in the integrated circuit IC itself. Examples of integrated circuits IC equipped with an antenna are the RFID circuits (acronym of “Radio Frequency Identification”) or Smart Cards, that are low power integrated circuits (low power ICs), that can be supplied and exchange information by using electromagnetic waves through wireless channels (and thus without contact or contactless) that use an electromagnetic coupling obtained through at least two antennas.
In any case, the antennas of the embedded type, nowadays used for RFID or Smart Cards, have a limited communication range due to their sizes.
Electrodes for capacitive type transmission are also known, that use the generic pad of an integrated circuit IC as an armature of a capacitor, thus allowing a wireless probing.
A method and an apparatus for probing an integrated circuit through capacitive coupling are described for instance in the U.S. Pat. No. 6,600,325 in the name of Coates et al. According to this document, a system that performs electrical testing of a device by placing a probe conductor in proximity to (but not touching) a target conductor within the device is described.
US patent application published under No. US 2008/0018350 in the name of Chao et al. describes an apparatus for testing integrates circuits with ultra-fine pitch based on a passive interposer to adapt probe card sizes to pad sizes, still using a contact approach.
A similar solution is proposed by M. Daito et al in the paper 7.6 presented at ISSCC 2010 (page 144 of the IEEE proceeding) entitled “Capacitively Coupled Non-Contact Probing Circuits for Membrane Based Wafer Level Simultaneous Testing”. A passive interposer is proposed to adapt the different pitches of a standard contact probe card and the DUT pads but in this solution a contactless approach is proposed to avoid the interconnect congestion.
Thus, it is highlighted that the contact solutions have different problems tied to the fact that the probe tips and the pads are damaged during the contact scrub of the probes and that the probe weight limits the test parallelism. Moreover, the contactless solutions, namely comprising a passive interposer, show an additional delay attenuation due to the passive interposer which limit the performance of the system as a whole.